This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-293626, filed Sep. 27, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor apparatus that requires a mode setting operation, and more particularly to a semiconductor apparatus to which an operation mode is set on the basis of an input signal and a mode setting method for the semiconductor apparatus.
2. Description of the Related Art
The semiconductor apparatus has built-in plural sorts of test modes for a performance test executed by changing a voltage inside the apparatus and the like, and for a reliability test executed by adding stress and the like. Those test modes include a test of applying a surplus voltage to an element inside a chip, or a test of simultaneously selecting plural cells without depending on an external address.
In a conventional semiconductor apparatus having the test modes shown in FIG. 30, false generation and false suspension of a test mode signal due to a noise is prevented by using a high-voltage detection circuit and a low-voltage detection circuit.
Besides, in Jpn. Pat. Appln. KOKAI Publication No. 9-166648 discloses the above-mentioned semiconductor apparatus in its figures such as FIG. 1.
Two external terminals 101 and 102 being a terminal used for both normal operation and test operation are connected to an internal bus 117 via an inverter 103 and an inverter 106, respectively while being connected to a circuit group of a low-voltage detection circuit 104 and a high-voltage detection circuit 105 or to a circuit group of a low-voltage detection circuit 107 and a high-voltage detection circuit 108 for the test operation.
Here, output voltages S1 and S4 of the high-voltage detection circuits 105 and 108 become high in level when voltages V1 and V2 inputted from the external terminals 101 and 102 become higher than a source voltage Vcc, respectively. Output voltages S2 and S3 of the low-voltage detection circuits 104 and 107 become high in level when voltages V1 and V2 inputted from the external terminals 101 and 102 become lower than a ground voltage GND, respectively.
An output S2 from the high-voltage detection circuit 105 and an output S3 from the low-voltage detection circuit 107 are inputted to an AND circuit 109, and an output S1 from the low-voltage detection circuit 104 and an output S4 from the high-voltage detection circuit 108 are inputted to an AND circuit 110. The output S5 from the AND circuit 109 is inputted to a set input end of a flip-flop 111, and the output S6 from the AND circuit 110 is inputted to a reset input end of the flip-flop 111.
The external terminal 112 is inputted to the reset input end of the flip-flop 111. The output from the flip-flop 111 becomes a test mode signal T, and is supplied to a CPU 113, a program counter 114, a ROM 115, and a RAM 116 that are connected to each other by an internal bus 117.
After power charge, the voltage of the external terminal 112 is made high in level, and the flip-flop 111 is reset, initialized, and set to a user mode.
Then, when the voltage V1 of the external terminal 101 is made abnormally high and the voltage V2 of the external terminal 102 is made abnormally low in order to transit the mode from the user mode to the test mode, the output S2 from the high-voltage detection circuit 105 and the output S3 from the low-voltage detection circuit 107 both become high in level, and the output S5 from the AND circuit 109 becomes high in level. Here, the flip-flop 111 is set, the test mode signal T becomes high in level, and the mode changes to the test mode.
In the case where the mode is transited from the test mode to the user mode, when the voltage V1 of the external terminal 101 is made abnormally low and the voltage V2 of the external terminal 102 is made abnormally high, the output S1 from the low-voltage detection circuit 104 and the output S4 from the high-voltage detection circuit 108 both become high in level, and the output S6 from the AND circuit 110 becomes high in level. Here, the flip-flop 111 is reset, the test mode signal T becomes low in level, and the mode changes to the user mode.
In both the user mode and the test mode, even if a noise is given to the external terminals 101 and 102 at the same time from outside, the set state is not changed.
The conventional semiconductor apparatus as mentioned above has problems described below.
In a conventional test mode setting method, an external terminal for setting-up a test state is required for each of the necessary test modes so that there has been cases where it is not possible to meet the requirement when sorts of the required tests are diversified due to maximizing in size, speedup, and the like of the semiconductor apparatus.
Moreover, there has been a possibility that the test mode is set without the user""s intention. Especially in a circuit for judging once whether the input signal is higher or lower than a reference value that is set and fixed, there has been a high risk of causing a false operation reacting to a little noise such as a swing of the power or a swing of a signal line when the voltage being close to the reference value is given.
In the semiconductor storage apparatus, a stress test and the like for a circuit element or a memory cell is prepared in a reliability test, a screening test before shipping products or the like, and depending on the sort of the test, there are cases where data until the memory cell data are destroyed under a test mode state are obtained. There has been a possibility that, if such a test condition is falsely set under a state where the semiconductor storage apparatus is used in a normal way, destruction of the memory cell data occurs.
Moreover, in a conventional technique shown in FIG. 30, a negative voltage is used as a low-voltage level, and the negative voltage must be prepared for the test mode setting. If a reference potential of the negative voltage is set to (Vccxe2x88x92Vth), which is a threshold of a transistor, the negative reference voltage inclines greater to minus as a threshold voltage is set higher. When an absolute value of the negative reference voltage exceeds a forward voltage of a pn-junction of a source and a drain of the transistor, the negative voltage cannot be given anymore so that the test entry is not executed in a normal manner.
According to a first aspect of the present invention, there is provided a semiconductor apparatus comprising a first voltage detection circuit to which an input signal is inputted, configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher; a second voltage detection circuit to which the input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than a second reference potential, and output a second level signal if the potential of the input signal is judged to be lower; and an operation mode entry setting circuit configured to judge plural times whether or not output signals from the first and second voltage detection circuits coincide with predetermined levels in synchronization with an input clock signal, and make an enter of an operation mode if all of the judged-results show that the output signals coincide with the predetermined levels.
According to a second aspect of the present invention, there is provided a semiconductor apparatus comprising a first voltage detection circuit to which a first input signal is inputted, configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher; a second voltage detection circuit to which the first input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than a second reference potential, and output a second level signal if the potential of the input signal is judged to be lower; a third voltage detection circuit to which a second input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than the first reference potential, and output the first level signal if the potential of the input signal is judged to be higher; a fourth voltage detection circuit to which the second input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than the second reference potential, and output the second level signal if the potential of the input signal is judged to be lower; and an operation mode entry setting circuit configured to judge plural times whether or not the output signals from the first to fourth voltage detection circuits coincide with predetermined levels in synchronization with an input clock signal, and make an enter of an operation mode if all of the judged-results show that the output signals coincide with the predetermined levels.
According to a third aspect of the present invention, there is provided a semiconductor apparatus comprising a first voltage detection circuit to which a first input signal is inputted, configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher; a second voltage detection circuit to which the first input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than a second reference potential, and output a second level signal if the potential of the input signal is judged to be lower; a filter circuit connected to the first and the second voltage detection circuits, to which the output signals from the first and the second voltage detection circuits are inputted while a second input signal is inputted, configured to output the output signals from the first and the second voltage detection circuits on the basis of the second input signal; and an operation mode entry setting circuit configured to judge plural times whether or not the output signals from the first and second voltage detection circuits outputted from the filter circuit coincide with predetermined levels in synchronization with an input clock signal, and make an enter of an operation mode if all of the judge-results show that the signals coincide with the predetermined levels.
According to a fourth aspect of the present invention, there is provided a semiconductor apparatus comprising a first voltage detection circuit to which a first input signal is inputted, configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher; a second voltage detection circuit to which the first input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than a second reference potential, and output a second level signal if the potential of the input signal is judged to be lower; a third voltage detection circuit to which a second input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than the first reference potential, and output the first level signal if the potential of the input signal is judged to be higher; a fourth voltage detection circuit to which the second input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than the second reference potential, and output the second level signal if the potential of the input signal is judged to be lower; a first filter circuit connected to the first and the second voltage detection circuits, to which a output signals from the first and the second voltage detection circuits are inputted while a third input signal is inputted, configured to output the output signals from the first and the second voltage detection circuits on the basis of the third input signal; a second filter circuit connected to the third and the fourth voltage detection circuits, to which a output signals from the third and the fourth voltage detection circuits are inputted while the third input signal is inputted, configured to output the output signals from the third and the fourth voltage detection circuits on the basis of the third input signal; and an operation mode entry setting circuit configured to judge plural times whether or not the output signals from the first to fourth voltage detection circuits outputted from the first and the second filter circuits coincide with predetermined levels in synchronization with an input clock signal, and make an enter of an operation mode if all of the judged-results show that the signals coincide with the predetermined levels.
According to a fifth aspect of the present invention, there is provided a semiconductor apparatus comprising a first voltage detection circuit to which a first input signal is inputted, configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher; a second voltage detection circuit to which the first input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than a second reference potential, and output a second level signal if the potential of the input signal is judged to be lower; a filter circuit connected to the first and the second voltage detection circuits, to which the output signals from the first and the second voltage detection circuits are inputted while the second input signal is inputted, configured to output the output signals from the first and the second voltage detection circuits on the basis of the second input signal; and an operation mode entry setting circuit configured to make an enter of an operation mode on the basis of the output signal from the filter circuits.
According to a sixth aspect of the present invention, there is provided a semiconductor apparatus comprising a first voltage detection circuit to which a first input signal is inputted, configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher; a second voltage detection circuit to which the first input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than a second reference potential, and output the second level signal if the potential of the input signal is judged to be lower; a third voltage detection circuit to which a second input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than the first reference potential, and output the first level signal if the potential of the input signal is judged to be higher; a fourth voltage detection circuit to which the second input signal is inputted, configured to judge whether the potential of the input signal is higher or lower than the second reference potential, and output the second level signal if the potential of the input signal is judged to be lower; a first filter circuit connected to the first and the second voltage detection circuits, to which the output signals from the first and the second voltage detection circuits are inputted while a third input signal is inputted, configured to output the output signals from the first and the second voltage detection circuits on the basis of the third input signal; a second filter circuit connected to the third and the fourth voltage detection circuits, to which the output signals from the third and the fourth voltage detection circuits are inputted while the third input signal is inputted, configured to output the output signals from the third and the fourth voltage detection circuits on the basis of the third input signal; and an operation mode entry setting circuit configured to make an entry of a specific operation mode on the basis of the output signal from the first and the second filter circuits.
According to a seventh aspect of the present invention, there is provided a semiconductor apparatus comprising a voltage detection circuit to which an input signal is inputted, configured to judge whether a potential of the input signal is higher or lower than a predetermined reference potential, output a first level signal if the potential of the input signal is judged to be higher, and output a second level signal if the potential of the input signal is judged to be lower; and an operation mode entry setting circuit configured to judge plural times whether or not the output signal from the voltage detection circuit coincides with predetermined levels in synchronization with an input clock signal, and make an enter of an operation mode if all of the judged-results show that the signal coincides with the predetermined levels.
According to an eighth aspect of the present invention, there is provided a mode setting method for a semiconductor apparatus comprising judging plural times whether or not a relation in level between first and second reference potentials and an input signal potential coincides with a predetermined condition in synchronization with an input clock signal, and executing a mode entry operation if all of the judge-results show that the relation coincides with the predetermined condition; and selecting an operation mode on the basis of an mode selection signal after the mode entry operation.